1. Technical Field
The present invention relates to integrated circuit designs and, in particular, to oscillators and methods for phase-locked loops.
2. Description of the Related Art
Phase-locked loops (PLLs) are used for clock signal generation in a wide variety of applications including, but not limited to, microprocessor or application specific integrated circuit (ASIC) clocking, high-speed communications, wireless, and radar. Two key parameters of a PLL are the tuning range (i.e., the range of frequencies that can be generated) and the phase noise. Another key parameter is the physical area taken up by the PLL on the chip. For high-performance applications, phase noise requirements limit the choice of the core oscillator in the PLL to LC-tank only (i.e., an oscillator comprising an inductor and a capacitor). The standard alternative to an LC-tank is a ring oscillator. Although ring oscillators have a wide tuning range and small physical area, they do not demonstrate the low noise properties that some applications call for.
The LC-tank oscillator, exclusively used in high-performance applications throughout the industry, has two main drawbacks. First, it has a relatively large size and, second, its tuning range is typically limited to 30% or 50% at most. This range is insufficient for applications targeting multiple standards and data rates.
One solution to the problem is to have two or more LC-tank oscillators in the PLL with the ability to switch between them. A significant drawback to this approach is that it can dramatically increase the physical size of the PLL. Not only is each oscillator large by itself, but the oscillators must be placed at a significant distance from one another in order to avoid destructive coupling between resonators. This prior art configuration is shown in FIG. 1. The first oscillator 10 is disposed adjacent to a second oscillator 20. As shown, there is a significant separation between the two inductors 12 and 22, often as much as one full radius. Through the combination of the second inductor and the wasted space between conductors, the physical area taken up by the PLL is greatly increased.
An alternative prior art solution is to use switched inductors, as shown in FIG. 2. FIG. 2 depicts two loops, 31 and 32, with a switch 33 that short circuits loop 32 when engaged. In this case, the length of the inductive coil is increased by the use of additional loops, controlled by switches. Such an approach improves tuning without increasing the physical area of the design, but the introduction of switches to the inductor introduces an unacceptable level of noise.